Pcie Controller Driver Intel Xeon

Mar 01, 2018 Windows 10 Pro x64 The drivers which I was updating and seen quality improvement mentioned already after that are: Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) PCIe Controller (x16. Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) PCIe Controller (x16) - 1901. Download driver. Home Page / chipsets /. Download drivers for Intel (R) PCIe Controller (x16) - 1901 chipset, or download DriverPack Solution software for automatic driver download and update.

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Pcie Controller Driver Intel Xeon Windows 10

By Sreelekshmy Syamalakumari (Intel), published on February 18, 2014

This is a computer translation of the original content. It is provided for general information only and should not be relied upon as complete or accurate.

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1. Executive Summary
2. Introduction
3. Intel® Xeon® processor E7 V2 family enhancements
3.1 Intel® C104/102 Scalable Memory Buffer
3.2 Intel® Secure Key (DRNG)
3.3 Intel® OS Guard (SMEP)
3.4 Intel® Advanced Vector Extensions (Intel® AVX)
3.5 Advanced Programmable Interrupt Controller (APIC) Virtualization (APICv)
3.6 PCI Express Enhancements
3.7 New RAS features
4. Conclusion
Appendix
About the Author

1. Executive Summary

The Intel® Xeon® processor E7 V2 family, codenamed “Ivy Bridge EX”, is a 2, 4 or 8-socket platform based on Intel’s most recent microarchitecture. Ivy Bridge is the 22-nanometer shrink of the “Sandy Bridge” microarchitecture. This product brings additional capabilities for data centers: more cores, more memory bandwidth and extended Reliability, Availability and Serviceability (RAS) features. As a result, platforms based on this product family can yield up to 2X improvement in performance compared to the previous generation Intel Xeon processor E7 family. Additional features introduced (such as Intel® AVX, Intel® Secure Key, and RAS features) provide opportunities to create faster, more secure, and more resilient applications.

2. Introduction

The Intel Xeon processor E7 V2 family is based on Ivy Bridge EX microarchitecture, an enhanced version of the Sandy Bridge microarchitecture (http://software.intel.com/en-us/articles/intel-xeon-processor-e5-26004600-product-family-technical-overview). The platform supporting the Intel Xeon processor E7 V2 family is named “Brickland” This paper discusses the new features available compared to the previous generation Intel Xeon processor E7 family. Each section includes information about what developers need to do to take advantage of new features for improving application performance, security and reliability.

3. Intel Xeon processor E7 V2 family enhancements

Some of the new features that come with the Intel Xeon processor E7 V2 family include:

22-nm process technology
Intel® C104/102 Scalable Memory Buffer (a.k.a “Jordan Creek”)
Security: Intel® Secure Key (DRNG)
Security: Intel® OS Guard (SMEP)
Intel® Advanced Vector Extensions (Intel® AVX)
Virtualization: APIC Virtualization (APICv)
PCI Express* (PCIe): Support for atomic operation, x16 Non Transparent Bridge
New RAS features

Figure 1. The Intel® Xeon® processor E7-4800 V2 product family Microarchitecture

Figure 1 shows a block diagram of the 4-socket Intel Xeon processor E7-4800 V2 family microarchitecture. All processors in the family have up to 15 cores (compared to 10 cores in its predecessor), which bring additional computing power to the table. They also have 25% additional cache (37.5 MB), higher memory capacity and bandwidth. With the 22-nm process technology, the Intel Xeon processor E7 V2 family consumes less power, during idle periods, compared to its predecessor platform.

Table 1 shows a comparison of the Intel Xeon processor E7-4800 V2 product family features compared to its predecessor, the Intel Xeon processor E7-4800.

Table 1. Comparison of the Intel® Xeon® processor E7–4800 product family to the Intel® Xeon® processor E7–4800 V2 product family

On Jordan Creek based platforms, exact memory speeds will depend on the memory configuration and population rules as well as the memory controller mode selected in the BIOS (Performance or Lockstep)

The rest of this paper discusses some of the main enhancements in this product family.

3.1 Intel® C104/102 Scalable Memory Buffer

The C104/102 scalable memory buffer available for Intel Xeon processor E7 V2 platforms significantly increase memory capacity – with 24 DDR3 DIMMs (64 GB) per socket, it is possible to support up to 6TB in a 4 socket platform. The Intel Xeon processor E7 V2 family supports up to 1600 MHz DDR3 speeds. There are 2 modes of operation for the memory controller – performance and lock step mode. Performance mode is the normal (default) mode of operation with higher I/O and bandwidth. Lockstep Memory mode uses two memory channels at a time, stores half the cacheline in one DIMM on one channel and the other half on the next, and offers an even higher level of protection. In lockstep mode, two channels operate as a single channel—each write and read operation moves a data word two channels wide. In three-channel memory systems, the third channel is unused and left unpopulated. The Lockstep Memory mode is the most reliable, but it reduces the total system memory bandwidth by one-third in most systems. This mode of operation will be configurable from the BIOS, and often the BIOS by default will be set to operate in ‘Performance’ mode.

3.2 Intel® Secure Key (DRNG)

Intel Secure Key (Digital Random Number Generator: DRNG) is a hardware approach to high-quality and high-performance entropy and random number generation. The entropy source is thermal noise within the silicon.

Figure 2. Digital Random Number Generator using RDRAND instruction

Figure 2 shows a block diagram of the Digital Random Number Generator. The entropy source outputs a random stream of bits at the rate of 3 GHz that is sent to the conditioner for further processing. The conditioner takes pairs of 256-bit raw entropy samples generated by the entropy source and reduces them to a single 256-bit conditioned entropy sample. This is passed to a deterministic random bit generator (DRBG) that spreads the sample into a large set of random values, thus increasing the amount of random numbers available by the module. DRNG is compliant with ANSI X9.82, NIST, and SP800-90 and certifiable to FIPS-140-2.

Since DRNG is implemented in hardware as a part of the processor, both the entropy source and DRBG execute at processor clock speeds. There is no system I/O required to obtain entropy samples and no off-chip bus latencies to slow entropy transfer. DRNG is scalable enough to support heavy server application workloads and multiple VMs.

DRNG can be accessed through a new instruction named RDRAND. RDRAND takes the random value generated by DRNG and stores it in a 16-bit or 32-bit destination register (size of the destination register determines size of the random value). RDRAND can be emulated via CPUID.1.ECX[30] and is available at all privilege levels and operating modes. Performance of RDRAND instruction is dependent on the bus infrastructure; it varies between processor generations and families.

Software developers can use the RDRAND instruction either through cryptographic libraries (OpenSSL* 1.0.1) or through direct application use (assembly functions). The Intel® Compiler (starting with version 12.1), Microsoft Visual Studio* 2012, and GCC* 4.6 support the RDRAND instruction.

Microsoft Windows* 8 uses the DRNG as an entropy source to improve the quality of output from its cryptographically secure random number generator. Linux* distributions based on the 3.2 kernel use DRNG inside the kernel for random timings. Linux distributions based on the 3.3 kernel use it to improve the quality of random numbers coming from /dev/random and /dev/urandom, but not the quantity. That being said, Red Hat Fedora* Core 18 ships with the rngd daemon enabled by default, which will use DRNG to increase both the quality and quantity of random numbers in /dev/random and /dev/urandom.

For more details on DRNG and RDRAND instruction, refer to the Intel DRNG Software Implementation Guide.

3.3 Intel® OS Guard (SMEP)

Intel OS Guard (Supervisor Mode Execution Protection: SMEP) prevents execution out of untrusted application memory while operating at a more privileged level. By doing this, Intel OS Guard helps prevent Escalation of Privilege (EoP) security attacks. Intel OS Guard is available in both 32-bit and 64-bit operating modes and can be enumerated via CPUID.7.0.EBX[7].

Figure 3. Pictorial description of Intel® OS Guard operation

Support for Intel OS Guard needs to be in the operating system (OS) or Virtual Machine Monitor (VMM) you are using. Please contact your OS or VMM providers to determine which versions include this support. No changes are required at the BIOS or application level to use this feature.

3.4 Intel® Advanced Vector Extensions (Intel® AVX)

Intel®AVX, a new-256 bit instruction set extension designed for applications that are floating-point (FP) intensive. This product family also introduces a new set of instructions to convert between single-precision and half-precision floating-point formats.

Figure 4. Intel® Advanced Vector Extensions Instruction Format

Intel AVX introduces the following architectural enhancements:

Support for 256-bit wide vectors and SIMD register set.
Instruction syntax support for generalized three-operand syntax to improve instruction programming flexibility and efficient encoding of new instruction extensions.
Enhancement of legacy 128-bit SIMD instruction extensions to support three-operand syntax and to simplify compiler vectorization of high-level language expressions.
Instruction encoding format using a new prefix (referred to as VEX) to provide compact, efficient encoding for three-operand syntax, vector lengths, compaction of SIMD prefixes and REX functionality.
FMA extensions and enhanced floating-point compare instructions add support for IEEE-754-2008 standard.

Intel AVX employs an instruction encoding scheme using a new prefix (known as a “VEX” prefix). Instruction encoding using the VEX prefix can directly encode a register operand within the VEX prefix. This supports two new instruction syntaxes in Intel 64 architecture:

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A non-destructive operand (in a three-operand instruction syntax): The non-destructive source reduces the number of registers, register-register copies and explicit load operations required in typical SSE loops, reduces code size, and improves micro-fusion opportunities.
A third source operand (in a four-operand instruction syntax) via the upper 4 bits in an 8-bit immediate field.

Two-operand instruction syntax previously expressed as
ADDPS xmm1, xmm2/m128
now can be expressed in three-operand syntax as
VADDPS xmm1, xmm2, xmm3/m128

In four-operand syntax, the extra register operand is encoded in the immediate byte. The introduction of three-operand and four-operand syntaxes helps to reduce the number of register to register copies, thus making the programming more efficient.

Intel AVX also brings some new data manipulation and arithmetic compute primitives, including broadcast, permute, fused-multiply-add, etc

Intel AVX improves performance due to wider vectors, new extensible syntax, and rich functionality which results in better data management. Applications that could benefit from Intel AVX include general purpose applications like image, audio/video processing, scientific simulations, financial analytics and 3D modeling and analysis.

Operating system and compiler support are needed for executing applications with Intel AVX. Some of the supporting operating systems include Linux* 2.6.30 or later, Windows 7* SP1 or later and Windows* 2008 server SP1 or later. The compilers supporting Intel AVX include Intel C/C++ and Fortran Compilers version 11.1 or later, Microsoft* Visual Studio 2010 or later and GCC* 4.4.1 or later.

There are a couple of ways a developer can make use of Intel AVX in their applications:

Re-compiling the application with the appropriate compiler – if the developer doesn’t want to modify his code, he can re-build his application using the appropriate compiler (mentioned above) using the right switches to turn on AVX optimizations. On Windows, using the Intel compiler, use the command line switch /QxAVX. On Linux, use –xavx. The switches /QaxAVX (Windows) and –axavx (Linux) may be used to build applications that will take advantage of AVX instructions on Intel systems that support these, but will use only SSE instructions on other Intel or compatible, non-Intel systems. For Microsoft Visual Studio compiler, use the flag /arch:AVX to enable AVX optimizations.
Hand-optimizing the application using intrinsics – the developer could modify relevant portions of his software code using intrinsic instructions. Please refer to http://software.intel.com/en-us/articles/intel-intrinsics-guide for more details on the intrinsics. The Intel® C++ Compiler supports Intel AVX-based intrinsics via the header file immintrin.h.

To best illustrate how AVX can be used, here is an example of how AVX was used to significantly improve performance of a financial services application: http://software.intel.com/en-us/articles/case-study-computing-black-scholes-with-intel-advanced-vector-extensions

For more details on Intel AVX, please go to http://software.intel.com/en-us/avx

3.5 Advanced Programmable Interrupt Controller (APIC) Virtualization (APICv)

A significant amount of performance overhead in machine virtualization is due to Virtual Machine (VM) exits. Every VM exit can cause a penalty of approximately 2,000 – 7,000 CPU cycles (see Figure 5), and a significant portion of these exits are for APIC and interrupt virtualization. Whenever a guest operating system tries to read an APIC register, the VM has to exit and the Virtual Machine Monitor (VMM) has to fetch and decode the instruction.

The Intel Xeon processor E7 V2 family introduces support for APIC virtualization (APICv); in this context, the guest OS can read most APIC registers without requiring VM exits. Hardware and microcode emulate (virtualize) the APIC controller, thus saving thousands of CPU cycles and improving VM performance.

Figure 5. APIC Virtualization

This feature must be enabled at the VMM layer: please contact your VMM supplier for their roadmap on APICv support. No application-level changes are required to take advantage of this feature.

3.6 PCI Express Enhancements

The Intel Xeon processor E7 V2 family supports PCIe atomic operations (as a completer). Today, message-based transactions are used for PCIe devices, and these use interrupts that can experience long latency, unlike CPU updates to main memory that use atomic transactions. An Atomic Operation (AtomicOp) is a single PCIe transaction that targets a location in memory space, reads the location’s value, potentially writes a new value back to the location, and returns the original value. This “read-modify-write” sequence to the location is performed atomically. This is a new operation added per PCIe Specification 3.0. FetchAdd, Swap, and CAS (Compare and Swap) are the new atomic transactions.

The benefits of atomic operations include:

Lower overhead for synchronization
Lock-free statistics (e.g. counter updates)
Performance enhancement for device drivers

The Intel Xeon processor E7 V2 family also supports X16 non transparent bridge. All these contribute to better I/O performance.

These PCIe features are inherently transparent and require no application changes.

For more details on these PCIe features, refer to:

3.7 New RAS features

PCIe Live Error Recovery (LER) - When errors are detected by the PCIe root port, the Live Error Recovery (LER) feature will bring down the PCIe link associated with the affected root port within one cycle and then automatically recover the link. PCIe LER also protects against the transfer of associated corrupt data during this process. PCIe LER allows the system to recover from PCIe errors that would otherwise cause the system to crash. Note that this is implemented in the hardware and there is no need to change anything in the software programs.
Machine Check Architecture (MCA) recovery – Execution Path – This enables software layers (OS, VMM, DBMS, and Application) to assist in system recovery from data errors that are not correctable at the hardware level. Execution path extends prior recovery capabilities to include errors detected in data passed to the CPU. MCA recovery allows the system to recover from certain errors that would otherwise be fatal. Execution path enabling greatly increases a number of situations where recovery is possible by extending this capability to data errors detected in the execution engine (core).
Enhanced Machine Check Architecture (eMCA) Gen 1 - Enhanced MCA is a new Xeon RAS capability that allows firmware to enhance the error logging capabilities of Machine Check Architecture. Enhanced MCA can be configured to provide more information to the software layer about error conditions enabling better recovery and better error identification. In Gen1 this information is provided for corrected memory errors and uncorrected errors. eMCA Gen 1 provides enhanced error log information to the OS, VMM, DBMS that can be used to extend software recovery capabilities and to provide better diagnostic and predictive failure analysis for the system. This enables higher levels of uptime and reduced service costs.
Machine Check Architecture (MCA) recovery for I/O - MCA recovery for IO incorporates PCIe uncorrected (non-fatal and fatal) errors into the architecturally supported MCA mechanism for communicating error information to the software layer (OS, VMM, DBMS) to improve error identification and recovery. MCA recovery for I/O enables the system to recover from I/O error conditions that would otherwise have been fatal, increasing overall uptime. It also provides additional diagnosis information on the source of errors which can reduce service costs.

The new RAS features require additional enabling. Please refer to the Appendix for the supported Operating Systems and VMMs that support these new features.

4. Conclusion

In summary, the Intel Xeon processor E7 V2 family, combined with the Brickland platform, provides many new and improved features that could significantly change your performance and power experience on enterprise platforms. Developers can make use of most of these new features without making any changes to their applications.

Appendix

Figure 6: Intel® Xeon® Processor E7 Family RAS Features OS Support Summary
** New features will be supported in upcoming OS releases. Please contact OS vendors for additional details
¥ denotes new features.

Figure 7: Intel® Xeon® Processor E7 Family RAS Features Virtualization (VMM) Support Summary
** Additional features will be supported in upcoming releases. Please contact vendors for additional details
¥ denotes new features.

About the Author

Sree Syamalakumari is a software engineer in the Software & Service Group at Intel Corporation. Sree holds a Master's degree in Computer Engineering from Wright State University, Dayton, Ohio.

Intel, the Intel logo, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries.
Copyright © 2014 Intel Corporation. All rights reserved.
*Other names and brands may be claimed as the property of others.

For more complete information about compiler optimizations, see our Optimization Notice.

(Redirected from Intel Xeon chipsets)

Around the time that the Pentium III processor was introduced, Intel's Xeon line diverged from its line of desktop processors, which at the time was using the Pentium branding.

The divergence was implemented by using different sockets; since then, the sockets for Xeon chips have tended to remain constant across several generations of implementation.

The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link. The I/O controller hub on the other hand, connects to lower-speed I/O, such as SATA, PCI, USB, and Ethernet.

1P6-based Xeon chipsets
2NetBurst-based Xeon chipsets
3Core-based Xeon chipsets
4Nehalem-based Xeon chipsets
5Sandy Bridge-based Xeon chipsets
6Ivy Bridge-based Xeon chipsets
7Haswell-based Xeon chipsets
8Skylake-based Xeon chipsets

P6-based Xeon chipsets[edit]

Dual processor P6-based Xeon chipsets[edit]

Intel's initial preferred chipset for Pentium III Xeon was the 840.

Product name	Codename	Processor FSB supported	Memory type supported	High-speed interfaces provided	Preferred IOCH
440GX AGPset	Marlinespike	100	One 72-bit-wide channel of SDRAM, with ECC; up to four DIMMs	PIIX4E
840	Carmel	100 or 133	Two channels RDRAM, two RIMMs per channel

Four processor P6-based Xeon chipsets[edit]

The Pentium III Xeon bus protocol allowed four processors on the same bus, so the 440GX AGPset could be used in four-CPU systems; the limit of 2GB of main memory remained. These support Slot 2.

There was also the 450NX PCIset, which consisted of several chips: a single 82451NX Memory and IO Bridge Controller roughly analogous to the North Bridge, up to two 82454NX PCI Expander Bridges which converted the protocol used by 451NX to two 32-bit PCI33 or one 64-bit PCI33 bus, along with up to two memory cards each equipped with one 82452NX RAS/CAS Generator chip and two 82453NX Data Path Multiplexer chips. It supported PIIX3 and PIIX4E south bridges, and EDO DRAM.

Eight processor P6-based Xeon chipset[edit]

In August 1999 Intel began shipping the Profusion PCIset.^[1] The chipset was based on technology developed by the Corollary company, which Intel acquired.^[2] It supported up to 8 Pentium III Xeon processors on two busses and maintained cache coherency between them.^[3]^[4]^[5] Profusion supported up to 32 GB of memory. It saw some limited competition from the NEC Aqua II chipset.^[6] Another minor player in the eight-way space was Axil Computer's NX801,^[2] which was used in an 8-way (two buses) Pentium Pro design, commercialized by Data General as their AV-8600 computer.^[7]

NetBurst-based Xeon chipsets[edit]

Dual processor NetBurst-based Xeon chipsets[edit]

E7500 corresponded to the first Northwood-based Pentium4 Xeons, E7501 is essentially identical but supports faster FSB and memory. The E7320, E7520 and E7525 chipsets correspond to Prescott-based Pentium4 Xeons, and differ mainly in their PCI Express support. These support Socket 604.

Product name	Codename	Processor FSB supported	Memory type supported	High-speed interfaces provided	Preferred IOCH
E7205	Granite Bay	400 or 533 MHz	Two channels of DDR at 100 MHz or 133 MHz	AGP 8× port, single 32-bit 33 MHz PCI bus, 266 MHz 8-bit hub interface for ICH4	ICH4
E7210^[8]	Canterwood-ES	400 MT/s, 533 MT/s or 800 MT/s	Two channels of unbuffered ECC and non-ECC DDR DIMMs (registered ECC is not supported) at 133 MHz, 166 MHz or 200 MHz (DDR-266/333/400)	66 MHz CSA interface for Gigabit LAN. MCH is connected to ICH via 66 MHz 8-bit (266 MT/s) Hub Interface v1.5. A 6300ESB ICH provides up to four 32-bit and/or 64-bit PCI-X at 33 or 66 MHz. Intel E7210 is server variant of 875P (Socket 478) without AGP, it can be used in dual Socket 604 configurations.^[9]	6300ESB
E7320^[10]	Lindenhurst VS	800 MHz	Two channels of registered DDR-333 or DDR2-400 SDRAM	One ×8 PCI Express interface with max theoretical bandwidth of 4 GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.	6300ESB, or 82801ER (ICH5R)
E7500	Plumas	400 MHz	Two channels of ECC DDR SDRAM at 100 MHz (3.2GB/s peak)	Three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH3-S	ICH3-S
E7501	Plumas	533 MHz	Two channels of ECC DDR SDRAM at 133 MHz (4.2GB/s peak)	Three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH3-S	ICH3-S
E7505	Placer^[11]	533 MHz	Two channels of ECC DDR SDRAM at 133 MHz (4.2GB/s peak)	AGP 8× port, three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH4	ICH4
E7520^[12]	Lindenhurst	800 MHz	Two channels of registered DDR-333 or DDR2-400 SDRAM	Three ×8 PCI Express interfaces each with max theoretical bandwidth of 4 GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.	6300ESB, or 82801ER (ICH5R)
E7525^[13]	Tumwater	800 MHz	Two channels of registered DDR-333 or DDR2-400 SDRAM	One ×16 and one ×8 PCI Express interface. A 6700PXH can be attached.	6300ESB, or 82801ER (ICH5R)

Note that the 82870P2 chips mentioned above were initially designed for the Intel 870 chipset for Itanium 2, and that the summary page of the E7320 datasheet incorrectly claims three PCI Express interfaces.

Quad processor NetBurst-based Xeon chipsets[edit]

Product name	Codename	Processor FSB supported	Memory type supported	High-speed interfaces provided	Preferred IOCH
E8500	Twin Castle	667 MHz	DDR-266, DDR-333 or DDR2-400	three ×8 and one ×4 PCI Express interface	82801EB (ICH5), or 82801ER (ICH5R)
E8501	Twin Castle	667 and 800 MHz	DDR2-400	82801EB (ICH5), or 82801ER (ICH5R)

Core-based Xeon chipsets[edit]

Single processor Core-based Xeon chipsets[edit]

Product name	Codename	Processor FSB supported	Memory type supported	High-speed interfaces provided	Preferred IOCH
3000	Mukilteo	533 or 800 or 1066 MHz	Two channels of ECC DDR2-533 or DDR2-667	PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH7	ICH7
3010	Mukilteo 2	533 or 800 or 1066 MHz	Two channels of ECC DDR2-533 or DDR2-667	PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH7	ICH7
3200	Bigby	800 or 1066 or 1333 MHz	Two channels of ECC DDR2-667 or DDR2-800	PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH9	ICH9
3210	Bigby	800 or 1066 or 1333 MHz	Two channels of ECC DDR2-667 or DDR2-800	PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH9	ICH9

Dual processor Core-based Xeon chipsets[edit]

These chipsets use a 'dual independent bus' design, in which each socket has its own connection to the chipset. These support LGA 771.

Product name	Codename	Processor FSB supported	Memory type supported	High-speed interfaces provided	Preferred IOCH
5000P	Blackford	1066, 1333	Four channels of FB-DIMM at 533 or 667 MHz	Two PCIe ×8 ports, plus two ×4 ports for communication with IOCH	631xESB or 632xESB
5000V	Blackford	1066, 1333	Two channels of FB-DIMM at 533 or 667 MHz	No PCI-e ports are exposed - connection is exclusively to the IOCH	631xESB or 632xESB
5000Z	Blackford	1066, 1333	Two channels of FB-DIMM at 533 or 667 MHz	One PCI-e ×8 port, plus two ×4 ports for communication with IOCH	631xESB or 632xESB
5000X	Greencreek	1066, 1333 (has a snoop filter, comprising about 1MB of SRAM, to keep cache coherency traffic between the two sockets from appearing on the external bus)	Four channels of FB-DIMM at 533 or 667 MHz	One PCI-e ×16 port	631xESB or 632xESB
5100	San Clemente	1066, 1333	Two channels of registered ECC DDR2	6 PCIe ×4 ports	631xESB or 632xESB
5400	Seaburg	1066, 1333, 1600; has a more advanced snoop filter than 5000X, comprising about 1.6MB of SRAM	Four channels of FB-DIMM at 533, 667 or 800 MHz	9 PCIe ×4 ports	631xESB or 632xESB

Four processor Core-based Xeon chipsets[edit]

This chipset uses four independent buses, and is used by the Tigerton and Dunnington processors.

Launch name	Codename	FSB speed	Memory speed	Fast I/O	IOCH
7300^[14]	Clarksboro	1066. Very sophisticated snoop filter, comprising 4.5MB of SRAM.	Four channels of FB-DIMM at 533 or 667 MHz	7 PCIe ×4 ports, of which two are usually used to connect to the IOCH	631x or 632x

Nehalem-based Xeon chipsets[edit]

Single processor Nehalem-based Xeon chipsets[edit]

The 3450 chipset is also compatible with an Intel Core i5 or Intel Core i3 processor.

Pcie controller driver intel xeon windows 10

Product name	Codename	DMI	Fast I/O	Other features
3400	Ibex Peak	1.0, 100 MHz	PCI Express 6 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor	8× USB 2.0, 4× SATA, Integrated LAN
3420	Ibex Peak	1.0, 100 MHz	PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor	12× USB 2.0, 6× SATA, Integrated LAN
3450	Ibex Peak	1.0, 100 MHz	PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor	14× USB 2.0, 6× SATA, Integrated LAN

Dual processor Nehalem-based Xeon chipsets[edit]

The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset. This means that the 5500 and 5520 (initial codename Tylersburg-EP) chipsets are essentially QPI to PCI Express interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity

Launch name	Codename	QPI ports	QPI speed	Fast I/O	IOCH	Other features
5500	Tylersburg-24S, Tylersburg-24D^[15]	1, 2	4.8, 5.86 or 6.4 GT/s	1 ×16 PCIe Gen 2, 2 ×4 PCIe Gen 1 to talk to southbridge	ICH10 (ICH9 also possible)	Integrated Management Engine with its own 100 Mbit Ethernet ^[16]
5520	Tylersburg-36S, Tylersburg-36D	1, 2	4.8, 5.86 or 6.4 GT/s	2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge	ICH10 (ICH9 also possible)	Integrated Management Engine with its own 100 Mbit Ethernet^[16]

Four processor Nehalem-based Xeon chipsets[edit]

Launch name	Codename	QPI ports	QPI speed	Fast I/O	IOCH	Other features
7500	Boxboro	2	6.4 GT/s	2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge	ICH10 (ICH9 also possible)	Integrated Management Engine with its own 100 Mbit Ethernet

Sandy Bridge-based Xeon chipsets[edit]

Single processor Sandy Bridge-based Xeon chipsets[edit]

The Intel C200 series chipsets that support the Intel Xeon E3-1200 CPU family.^[17]^[18]

Product name	Codename	DMI	Fast I/O	Other features
C202	Cougar Point	2.0, 100 MHz	PCI Express 8 × 1 ports, single 32-bit 33 MHz PCI bus, DMI for processor	12 × USB 2.0, 6 × SATA 1.5/3 Gbit/s, Integrated LAN
C204				12 × USB 2.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN
C206				14 × USB 2.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated Graphics, Intel Anti-Theft Technology, Active Management Technology 7.0

Intel Pci Simple Controller Driver

Dual processor Sandy Bridge-based Xeon chipsets[edit]

The Intel C600 series chipsets support the Intel Xeon E5-2600 CPU family. Common to all C600 variants are the following features:

DMI interface to CPU at 20 GT/s
8 PCIe 2.0 (5 GT/s) lanes, configurable by the board manufacturer as 8×1, 4×2, 2×4, or 1×8.
2 SATA ports supporting 6/3/1.5 gigabaud operation
4 SATA ports supporting 3/1.5 gigabaud operation
one PCI 2.3 32-bit 33 MHz bus interface
14 USB 2.0 ports
single-port Gigabit Ethernet controller
Active Management Technology 7.0 and Anti-Theft Technology
HD Audio controller

Some chipset variants have additional mass storage interfaces:

Product name	Codename	additional mass storage capabilities
C602J	Patsburg	none
C602		4× SATA 1.5/3 gigabaud ports
C604		4× SAS/SATA 1.5/3 gigabaud ports
C606		8× SAS/SATA 1.5/3 gigabaud ports optionally through dedicated PCIe 2.0 ×4 (5 GT/s) interface, 1 additional SMBus
C608		8× SAS/SATA 1.5/3 gigabaud ports optionally through dedicated PCIe 2.0 ×4 (5 GT/s) interface, 2 additional SMBus

Dual processor Gladden/Sandy Bridge-EP/EN-based Xeon chipsets[edit]

The Intel Communications 8900 series chipsets that support the GladdenIntel Xeon E3-11xx^[19] or Sandy Bridge-EP/ENIntel Xeon E5-2xxx^[20] CPU families.

Product name	Codename	DMI	Fast I/O	Other features
DH8900	Cave Creek	2.0, 100 MHz	PCI Express 2.0 ×16 + PCI Express 1.0 4 × 1 ports, DMI for processor	6 × USB 2.0, 6 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN
DH8903			PCI Express 2.0 ×8 + PCI Express 1.0 4 × 1 ports, DMI for processor	6 × USB 2.0, 2 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN, 5 Gbit/s QuickAssist
DH8910			PCI Express 2.0 ×4 + PCI Express 1.0 4 × 1 ports, DMI for processor	6 × USB 2.0, 2 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN, 10 Gbit/s QuickAssist
DH8920			PCI Express 2.0 ×4 + PCI Express 1.0 4 × 1 ports, DMI for processor	6 × USB 2.0, 2 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN, 20 Gbit/s QuickAssist

Ivy Bridge-based Xeon chipsets[edit]

Single processor Ivy Bridge-based Xeon chipsets[edit]

The Intel C200 series chipsets that support the Intel Xeon E3-1200v2 CPU family.^[21]

Product name	Codename	DMI	Fast I/O	Other features
C216	Panther Point	2.0, 100 MHz	PCI Express 2.0 8 × 1 ports, single 32-bit 33 MHz PCI bus, DMI for processor	4 × USB 3.0 + 14 × USB 2.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated Graphics, Intel Anti-Theft Technology, Active Management Technology 8.0

Haswell-based Xeon chipsets[edit]

Intel Pci Driver Download

Single processor Haswell-based Xeon chipsets[edit]

The Intel C220 series chipsets support the Intel Xeon E3-1200v3 CPU family.^[22]

Product name	Codename	DMI	Fast I/O	Other features
C222	Lynx Point	2.3, 100 MHz	Eight PCI Express 2.0 ×1 ports, DMI for processor	10 × USB 2.0/3.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated IDE, Rapid Storage Technology enterprise
C224				12 × USB 2.0/3.0, 4 × SATA 1.5/3/6 Gbit/s + 2 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated IDE, Rapid Storage Technology enterprise
C226				14 × USB 2.0/3.0, 6 × SATA 1.5/3/6 Gbit/s, Integrated LAN, Integrated Graphics, Rapid Storage Technology enterprise, Active Management Technology 9.0, Identity Protection Technology, VGA, Wireless Display

Skylake-based Xeon chipsets[edit]

Single processor Skylake-based Xeon chipsets[edit]

Intel Pci Controller Driver

The Intel C230 series chipsets support the Intel Xeon E3-1200v5 CPU family.

Both, the C232 and the C236 support the LGA 1151 socket.